1. Field of the Invention
This invention pertains generally to FPGA circuits, and more particularly to methods and circuits for adapting FPGA architecture in response to levels of anticipated process variation.
2. Description of Related Art
Modern VLSI design is significantly impacted from process variation as devices scale down to nanometer technologies. Variability in effective channel length, threshold voltage, and gate oxide thickness introduces uncertainties in both chip performance and power consumption. For example, measured variation in chip-level leakage can be as high as 20× compared to the nominal value for high performance microprocessors. In addition to meeting the performance constraint under timing variation, dice with excessively large leakage due to such a high variation have to be rejected to meet the given power budget.
Recent work has studied parametric yield estimation for both timing and leakage power. Statistical timing analysis considering path correlation has been studied, and both non-Gaussian and non-linear variation models introduced. In addition, timing yield estimation has been discussed in the art. As devices scale down, leakage power becomes a significant component of total power consumption and it is significantly affected by process variation. Numerous investigations into parametric yield have considered both leakage and timing variations. Power minimization by gate sizing and threshold voltage assignment under timing yield constrains have been studied. However, these studies focus on ASICs and do not consider these aspects with regard to other devices, specifically field programmable gate arrays (FPGA) devices.
A small number of recent papers have studied FPGA power modeling and optimization. In one study the leakage power of a commercial FPGA architecture was quantified, and in another a high level FPGA power estimation methodology was presented. Power evaluation frameworks were introduced for generic parameterized FPGA in a number of studies while it has been shown that both interconnect and leakage power are significant for FPGAs in nanometer technologies. Power optimization for FPGAs have also been studied. Region based power gating for FPGA logic blocks and fine grained power-gating for FPGA interconnects have been proposed, and Vdd programmability has been applied to both FPGA logic blocks and interconnects. Architecture evaluation has been performed first using the metrics of area and delay. For non-clustered FPGAs, it was shown that using lookup tables (LUT) with four input terms (LUT size of 4) achieves the smallest area and a LUT size of 5 or 6 leads to the best performance. Later on, the cluster-based island style FPGA was studied using the metric of area-delay product which indicated that LUT sizes ranging from 4 to 6 and cluster sizes between 4 and 10 can produce the best area-delay product. Besides area and delay, FPGA architecture evaluation considering energy was recently studied. In that study it was shown that in 0.35 μm technology, a LUT size of 3 consumes the smallest energy. In 100 nm technology, a LUT size of 4 consumes the smallest energy and a LUT size of 7 leads to the best performance. Another investigation further evaluated the architecture for the FPGAs with field programmable dual-Vdd and power gating considering area, delay, and energy. A most recent work showed that device and architecture co-optimization is able to obtain the largest improvement in FPGA performance and power efficiency. Compared to the baseline, device and architecture co-optimization can reduce energy-delay product by 18.4% and chip area by 23.3%.
However, all the above FPGA power and delay evaluation work is involved with deterministic value and does not consider process variations.
Although FPGA architectures are characterized with substantial regularity, and thus less subject to process variation than ASICs, the parametric yield for FPGAs is still in need of study.
Accordingly, a need exists for FPGA circuit architectures and methods for improving leakage yield and timing yield in response to analyzing process variations. These needs and others are met within the present invention, which overcomes the deficiencies of previously developed FPGA circuit architectures and methods.